The invention relates to switches and switch stages forming part of telecommunication systems. More specifically, the invention relates to establishing connections through digital circuit-switching switches.
User data switched through a digital switch belong to channels, so called connections. In the switch, user data originating from each connection from a respective input in the switch are switched to a respective selectable output in the switch. A technique used in connection thereto is circuit switching. A common switch structure in circuit switching is called "Time Space Time" (TST). In switches having this structure, a plurality of time switch stages are connected to a space switch stage. User data is first switched through an incoming time switch stage, then through a space switch stage and finally through an outgoing time switch stage.
User data from several connections that are to be switched through a switch of TST-structure are multiplexed by means of time multiplexing. In time multiplexing, the user data is placed in time slots that are arranged in frames. In switching the user data through the switch, it is moved between different time slots and frames. This is accomplished by delaying the user data in memories, so called speech memories, in the time switch stages of the switch. A speech memory comprises storage positions for storing user data. Each storage position corresponds to a time slot and stores, during a certain time, a data word of the user data, such as a byte. In addition to the speech memories, the time switch stages also include control memories and time slot counters by means of which writing of the user data into, and reading of the user data out of the speech memories are performed in different time slots. A control memory also includes storage positions, each of which corresponds to a time slot. A time slot counter cyclically addresses storage positions in the control memory as well as in the speech memory. For each time slot, a storage position in the control memory is addressed for reading control information stored in the control memory. The control information in the control memories in turn addresses the speech memories for reading the user data from the incoming time switch stages on one hand, and for writing the user data into the outgoing time switch stages on the other hand.
User data arriving to an incoming time switch stage appears in incoming time slots. In the space switch stage, the user data is placed by the incoming time switch stage in so called internal time slots. The user data going out from an outgoing time switch stage is placed by the outgoing time switch stage in outgoing time slots. Conflict in the space switch stage is avoided by means of the internal time slots.
Control information is generated in a control system, such as a computer program-controlled control system, being part of the telecommunication system. The control system is connected to the switch. Writing of control information into the control memories is instructed from the control system for assigning time slots used in the switching of the user data through the switch.
In one type of connection, a so called narrowband connection, user data arrives in a single incoming time slot each frame. User data are delayed differently for different narrowband connections. For each narrowband connection, the delay depends on in which incoming time slots that user data arrives to the switch, and in which internal time slots and outgoing time slots that user data for the narrowband connection are switched through the switch. The reciprocal timing relations between the incoming time slots, the internal time slots and the outgoing time slots for a narrowband connection determines the delay of the user data belonging to the narrowband connection.
Another type of connection, a so called wideband connection, occupies several time slots in each frame. User data belonging to a wideband connection arrives in several incoming time slots in each frame, and is switched through the switch in several internal time slots and in several outgoing time slots, in a sense as several separate narrowband connections. Thus, a wideband connection may be considered as an association of several narrowband connections. User data belonging to a wideband connection will consequently be switched through the switch in several narrowband connections with different delays.
A problem in connection thereto is to obtain sequence integrity, so called Time Slot Sequence Integrity (TSSI), and frame integrity, so called Time Slot Frame Integrity (TSFI), for wideband connections, i.e. to assure that data words constituting user data for a wideband connection maintain one and the same reciprocal time order through the switch on one hand, and that those data words that arrive in incoming time slots in one and the same frame are placed in the same frame in outgoing time slots on the other hand.
If as an example frame integrity (TSFI) is not preserved through the switch, then the user terminals in some telecommunication applications have to be equipped with frame analysis and frame regeneration equipment. This means an undesirable increased cost for the users.
U.S. Pat. 4,809,259 to Jonsson discloses an arrangement for establishing a wideband connection in a switching network. A marking device is disposed at the input of the switching network to provide markings in successive frames of the respective contents of the time slots utilized by the connection channels such that each affected time slot in a first frame is assigned a first marking and each affected time slot in a second frame is assigned a second marking. A scanning device is disposed at the output of the switching network to detect the markings such that a possible delay between the respective contents of the channels can be determined. Furthermore, the scanning device controls a delay equalizing device in the channels. The equalizing device comprises at least two paths for the flow of data from the switching network, a first path being a direct path without delay, a second path having a delay memory in the form of a register that delays data one frame, a third path delaying the data two frames, and so on. The scanning device provides delay instructions to a control memory in the equalizing device, and the delay instructions in the control memory control a selector which determines from which one of the paths data is to be read.
The Swedish Patent Publication SE-B-461,310 describes a method and device for switching a wideband connection through a digital time switch. The problem addressed in the Publication is that some time slots are delayed a frame, whereas other time slots are not delayed. According to the Swedish Patent Publication, a processor in the switch determines which outgoing time slots will hold information that is delayed one frame, and which outgoing time slots will hold information that is not delayed, and a control memory in the switch is provided with a marking bit, for each outgoing time slot, that indicates if the time slot is delayed or not. Incoming time slots to the digital time switch are sequentially written into a first speech memory. The first speech memory is connected to an additional separate speech memory, and the incoming time slots stored in the first speech memory are transferred to and written into the additional speech memory with a delay of one frame. During each clock pulse, information stored in a given storage position in the first speech memory is read from the first speech memory and written into the additional speech memory in a corresponding storage position, whereupon information in an incoming time slot in a subsequent frame is written into the first speech memory at the given storage position. Consequently, the additional speech memory will hold information that is delayed one frame relative to the contents of the first speech memory. For each outgoing time slot, information corresponding to the time slot is read from the first speech memory as well as from the additional speech memory and provided to a multiplexor. The multiplexor is controlled by the corresponding marking bit in the control memory, and connects a bus for outgoing time slots either to the first speech memory or to the additional speech memory. In this way, the information in delayed time slots will be read from the first speech memory and transferred onto the bus, and the information in non-delayed time slots will be read from the additional speech memory.
The solution of the Swedish Patent Publication SE-B-461,310 implies that all outgoing time slots are delayed an extra frame through the switch. The number of necessary memory accesses is increased considerably, since two write operations and two read operations are required for each time slot in the time switch. This increases the amount of dissipated power in the digital time switch. Read-out is performed only from the storage positions in the additional speech memory that are associated with a wideband connection. This means that a malfunctioning storage position in the additional speech memory is not detected until a wideband connection that utilizes that particular storage position is actually established. Consequently, it is not possible to continuously monitor the storage positions of the additional speech memory since parity check of the information in these storage positions can only be performed in connection with read-out onto the outgoing bus from positions associated with established wideband connections.
The European Patent Application 0,532,914 A2 relates to a delay correcting system in a multi-channel PCM-switching system. In accordance with this delay correcting system, an external memory separated from the speech memories in the switch structure itself, and a control unit for delaying some of the data stored in this external memory, are utilized. The external memory is provided at the output (or the input) of the switch, and the data that have been switched through the switch are stored after output therefrom in the external memory. The control unit generates frame correction information of several bits that is sent to a complicated circuit. The circuit functions to delay some of the data stored in the external memory in accordance with the frame correction information such that these data are delayed by the number of frames indicated by the most delayed data through the switch. Consequently, data in an outgoing frame N from the switch can be delayed one or more frames such that these data are outputted in frame N+1, N+2 or N+3.
According to the solution of the European Patent Application 0,532,914 A2, neither the external memory nor the circuit otherwise is integrated in the switch structure itself. In addition, the use of an additional external memory increases the number of necessary memory accesses. Besides, the additional external memory does not have any continuous monitoring of the storage cells, since these cells are used only in delay for established wideband connections and not for narrowband connections.
U.S. Pat. 4,704,716 to Bowers et al. discloses a method and device for establishing a wideband connection comprising a number of segments of TDM-channels through a communication network. In particular, a switching network of TST-type is provided with additional buffer memories in the incoming time stage and the outgoing time stage to assure that all data received in a time frame from a given segment is assembled only into the same outgoing time frame. In the incoming stage, two buffer memories are used, where all data in a given frame is stored in one of these buffer memories in a given frame period, at the same time as read-out of data in the other buffer memory is performed, and read out of the same buffer memory the next time period, at the same as data is stored in the other buffer memory. In the outgoing stage, where the read and write cycles of a time frame do not coincide because of signal delays in the switching network, three buffer memories are used in a way corresponding to that in the incoming time stage to assure that data in a given time frame are maintained in the same time frame.
This solution results in an extra delay in both the incoming stage and the outgoing stage. A plurality of additional buffer memories are required, and in addition, the writing and reading alternately between the different buffer memories have to be administered in some way.